Integration of a floating body memory on SOI with logic transistors on bulk substrate

ABSTRACT

A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon.

FIELD OF THE INVENTION

This invention relates to the field of integrated circuit memories,particularly those using transistors with floating bodies.

PRIOR ART AND RELATED ART

Most common dynamic random-access memory (DRAM) cells store charge on acapacitor and use a single transistor for accessing the capacitor. Morerecently, a cell has been proposed which stores charge in a floatingbody of a transistor. A back gate is biased to retain charge in thefloating body.

In one proposal, an oxide layer is formed on a silicon substrate and asilicon layer for the active devices is formed on the oxide layer (SOIsubstrate). The floating bodies are defined from the silicon layer; thesubstrate is used as a back or biased gate. One problem with thisarrangement is the relatively high voltage required on the back gatebecause of the thick oxide. One such structure is discussed inconnection with FIG. 1.

Several structures have been proposed to reduce the relatively high biaspotential discussed above, including use of a planar double gatefloating body and silicon pillars. These structures are difficult tofabricate. This and other related technology is described at C. Kuo,IEDM, December 2002, following M. Chan Electron Device Letters, January1994; C. Kuo, IEDM, December 2002, “A Hypothetical Construction of theDouble Gate Floating Body Cell;” T. Ohsawa, et al., IEEE Journal ofSolid-State Circuits, Vol. 37, No. 11, November 2002; and David M.Fried, et al., “Improved Independent Gate N type FinFET Fabrication andCharacterization,” IEEE Electron Device Letters, Vol. 24, No. 9,September 2003; Highly Scalable FBC with 25 nm BOX Structurefor EmbeddedDRAM Applications, T. Shino, IDEM 2004, pgs 265-268; T. Shino, IEDM2004, “Fully-Depleted FBC (Floating Body Cell) with enlarged signalWindow and excellent Logic Process Compatibility;” T. Tanaka, IEDM 2004,“Scalability Study on a Capacitorless 1T-DRAM: From Single-gate PD-SOIto Double-gate FinDRAM; U.S. patent application 2005/0224878; and“Independently Controlled, Double Gate Nanowire Memory Cell withSelf-Aligned Contacts,” U.S. patent application Ser. No. 11/321,147,filed Dec. 28, 2005.

Another floating body formed on a bulk substrate is described inSymposium on VLSI Technology Digest of Technical Papers, page 38, 2005by R. Ranica, et al. The floating p well, as described, is isolated fromneighboring devices by a shallow trench isolation region and underlyingn well.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional, elevation view of a prior art floating bodymemory fabricated on a silicon-on-insulator (SOI) substrate.

FIG. 2 is a cross-sectional, elevation view of a memory fabricated inaccordance with an embodiment of the present invention.

FIG. 3 is an alternate embodiment to the memory illustrated in FIG. 2.

FIG. 4 is a cross-sectional, elevation view of a SOI substrate, afterremoval of an overlying silicon and underlying insulator on the sectionsof the substrate used for logic devices in an integrated circuit memory.

FIG. 5A illustrates the substrate of FIG. 4 after epitaxial growth ofsilicon.

FIG. 5B illustrates an alternate process for providing the structure ofFIG. 5A.

FIG. 6 illustrates the substrate of FIG. 5A following several ionimplantation steps, formation of isolation regions, and formation ofsilicon bodies in the memory section of the integrated circuit. FIG. 6is taken generally through the section line 6-6 of FIG. 10.

FIG. 7 is a cross-sectional, elevation view corresponding to the pointin processing of FIG. 6, however for the logic section of the integratedcircuit.

FIG. 8 illustrates the structure of FIG. 6, following additional trenchisolation processing.

FIG. 9 illustrates the structure of FIG. 7, following additional trenchisolation processing.

FIG. 10 is a plan view of the integrated circuit memory used toillustrate the memory section of the integrated circuit and the contactfor biasing the floating body memory cells.

DETAILED DESCRIPTION

In the following description, a memory and method for fabricating thememory is described. Numerous specific details are set forth, such asspecific conductivity types, to provide a thorough understanding of thepresent invention. It will be apparent to one skilled in the art, thatthe present invention may be practiced without these specific details.In other instances, well known processing steps and circuits have notbeen described in detail, in order not to unnecessarily obscure thepresent invention.

Below, reference is made to a silicon-oxide-insulator (SOI) substrate.SOI substrates are well-known in the semiconductor industry. By way ofexample, they are fabricated by bonding a monocrystalline silicon layeronto a bulk silicon substrate and then planarizing the silicon layer sothat it is relatively thin. This relatively thin, low body effect SOIlayer is used for active devices. Other techniques are known for formingan SOI substrate including, for instance, implanting oxygen into asilicon substrate to form a buried oxide layer. The typical SOIsubstrate includes a bulk monocrystalline silicon substrate which isrelatively thick, a buried oxide (BOX) layer disposed on the bulksilicon, and the SOI layer, a relatively thin monocrystalline siliconlayer for active devices.

Prior Art Device of FIG. 1

In FIG. 1, a portion of an integrated circuit, such as a memory arraywith peripheral logic circuits, is illustrated disposed on an SOIsubstrate 12. The active devices are formed on the SOI layer 14 which isseparated from the bulk silicon substrate 15 by the BOX layer 13.

Several wells are formed in the bulk substrate 15 which are biasedappropriately to serve the device formed above the wells. Often, thebulk substrate is a p type substrate such as substrate 15 of FIG. 1. A pwell, sometimes referred to as a “plate” 16, is formed in the bulksubstrate and negatively biased to act as the back gate or back platefor floating body memory cells (FBCs). The bias on the plate 16 attractsholes in the FBCs, providing a capacitor-like storage for the DRAM cellsfabricated in the FBC array.

In the peripheral section of the integrated circuit, n wells such as nwell 18, and p wells such as p well 19, are implanted, and isolated fromthe bulk substrate by a deep n well 17. The n well 18 has p channeltransistors fabricated above it in the SOI layer, with the welltypically biased at the VCC potential (e.g. 3.8 volts). The p well 19,which is maintained at 0 volts, has n channel devices fabricated aboveit in the SOI layer.

One problem with the memory of FIG. 1 is that both the FBC array andlogic devices are fabricated on the SOI substrate. Consequently, the FBCand logic devices will have the same BOX. Substrates with thinner BOXoffer better charge retention for FBC due to stronger capacitivecoupling between the substrate and the floating body. The samecapacitive coupling, however, can cause high capacitance for logicdevices, which may degrade logic device performance for sufficientlythin BOX. Some processes are better suited for fabricating logic deviceson a bulk substrate so that the logic devices may be optimized forspecific applications such as high speed circuits and SRAM. In addition,circuit design methodology developed for bulk devices may be utilizedwhile capturing the benefit of FBC devices on SOI. As will be seenbelow, the present invention provides a solution to this problem.

Overview of Two Embodiments

Referring first to FIG. 2, an SOI substrate 20 is illustrated. Thesubstrate 20 has a p type monocrystalline silicon bulk substrate 21. Anintegrated circuit, such as a memory having a memory array andperipheral circuits using ordinary CMOS logic, is fabricated on the SOIsubstrate. However, the SOI layer is removed for the logic devices. Inthe embodiment of FIG. 2, a deep n well 23 is implanted in the p typebulk substrate and an overlying p well 24 is implanted within the n well23. These wells are disposed below those sections of the SOI layer wherea memory array is fabricated. As illustrated, the BOX layer 27 remainson the p well 24. Diffusion bodies 26 for FBCs are fabricated from theSOI layer.

In the sections of the integrated circuit where the logic devices arefabricated, the SOI layer and underlying oxide are removed and the bulksubstrate is epitaxially grown to a level approximately equal with thelevel of the SOI layer in the memory section. For the illustratedembodiment, fins 28 are fabricated from the bulk silicon in the p typebulk substrate, for n channel transistors. An n well 22 is implanted inthe p type bulk substrate and fins 29 are fabricated in this well forthe p channel transistors.

Consequently, the BOX layer 27 may be made relatively thin, and itsthickness optimized for the memory array without concern about thecapacitive coupling the thin oxide provides in the logic section of thememory or other integrated circuit. By removing the BOX layer 27 in thelogic area may provide additional benefits for some circuits, such as6-transistor SRAM, due to elimination of the floating body.

Note that in FIGS. 2 and 3 and the other figures, it is assumed thattri-gate n channel and p channel devices are fabricated in the logicsection from the fins. Planar CMOS devices may also be formed in thebulk silicon.

A different embodiment is shown in FIG. 3, where the well arrangement issimilar to the well arrangement shown in the prior art memory of FIG. 1.Again, here, a starting p type SOI substrate 30 is used. The bulksubstrate 31 is the back gate for the FBCs in the SOI layer. The SOIlayer is etched defining the diffusion bodies 36 for the FBCs. A deep nwell 33 is implanted in those sections of the bulk substrate where thelogic devices are to be fabricated. N wells 32 and p wells 34 areimplanted over and within the n well 33. Fins 38 for the p channeldevices are etched from the bulk silicon in the wells 32, and similarly,fins 39 are etched in the bulk silicon of the p wells 34 for the nchannel devices.

The wells in the bulk silicon for FIGS. 2 and 3 may be formed using ionimplantation as is well-known in the art. The wells can be formed as aninitial step in the processing before any fabrication occurs for thelogic or memory devices. Alternatively, the wells can be formed at alater stage in the processing, for instance, after the bodies and finshave been formed, or for that matter, at other points in the processing.

Processing of FIGS. 4-7

Referring to FIG. 4, an SOI substrate is used as a starting wafer forone embodiment. It includes the bulk monocrystalline silicon substrate40, typically doped with a p type dopant, a BOX layer 41, and anoverlying monocrystalline silicon (SOI) layer 42. A pad oxide is firstgrown or deposited on the silicon layer 42 (not shown). Then, a siliconnitride layer 43 is deposited over the pad oxide, and masked and etchedto protect those sections of the substrate where the memory array is tobe fabricated. After removing the exposed pad oxide, the silicon of theSOI layer can be dry or wet etched to stop at the underlying BOX layer41. A wet or dry etchant can be used to remove the BOX 41 where exposed,revealing the underlying bulk substrate 40. As shown in FIG. 4, thisleaves the exposed bulk silicon at a well-defined level below the levelof the SOI layer.

Now, a selective epitaxial growth of silicon is used to bring the bulksilicon in the logic sections up to the same level as the SOI layer.This is shown in FIG. 5A by the region 44 which has been grown from thebulk substrate 40 to a level approximately equal to the level of thesilicon in the memory array. With selective etches for silicon and oxideused for etching the SOI layer 42 and BOX 41, the step height betweenthe top surface of SOI layer 42 and the top surface of bulk substrate 40is very well controlled. Since the epitaxial growth of silicon also hasvery good control for film thickness, the top surface of SOI layer 42and the top surface of expitaxially grown silicon 44 can bewell-leveled. A planarization step may not be necessary but may be usedto make the two levels more closely matched. The planar structure isdesirable for patterning isolations.

The structure of FIG. 5A can be substantially produced with alternateprocessing shown in FIG. 5B. Here a bulk substrate (not SOI substrate)is used. Those areas where logic devices are to be fabricated arecovered with a photoresist or other material that block ions fromreaching the underlying substrate. Then the substrate is ion implantedwith oxygen at an energy level which implants ions beneath the surfaceas shown by the “XXX” layer in FIG. 5B. After annealing, the oxygenforms a buried silicon dioxide (BOX) layer in the bulk siliconsubstrate. This provides a surface layer of monocrystalline siliconisolated from the bulk substrate by a SiO₂ layer (SOI layer),substantially as shown in FIG. 5A.

At this point in the processing, or prior to this point or after thispoint, the wells shown in FIG. 2 or 3 can be formed in the bulksubstrate 40.

Now, a pad oxide layer 51 and a silicon nitride layer 50 are formed overthe silicon in both the SOI layer and bulk silicon substrate whereexposed. The nitride layer is masked and etched to define silicon bodiesfor the FBCs in the memory section that later will be implanted withsource and drain regions, as well as fins for the logic devices in thelogic section. The resulting bodies, along with isolation oxide 55,formed in a standard shallow trench isolation process, are shown inFIGS. 6 and 7.

Referring first to FIG. 6, it should be noted that the bodies 42 areisolated by the BOX layer 47 from the underlying substrate. Thus, thebodies 42 are truly floating, and when the p well 46 is biased, chargewill accumulate in the channel portion of the FBCs. In FIG. 7 it shouldbe noted that the fin 60 for the NMOS device extends from the p wells 58and is integral with the silicon in this well. Similarly, the fin 61 forthe PMOS device extends from, and is integral, with the n well 59.

Next as shown in FIGS. 8 and 9, after the nitride and pad oxide isremoved, the trench isolation regions 55 are etched back in the logicsection, and for the illustrated embodiment, not initially etched in thememory section. This allows planar devices in the memory area and finFETdevices or planar devices in the logic area. Typical FBC devices requirethicker gate oxide than the logic devices in the sub-100 nm regime. Thethicker gate oxide for FBC devices can be easily formed with typicaldual gate oxide process. For example, a thick gate oxide is grown on thewafer. The thick gate oxide is removed in the logic area by masking theFBC area. The wafer is then cleaned and a thin gate oxide is grownacross the wafer. The thin gate oxide may contain high k dielectric forthe logic devices. Thus, a different dielectric may be used for thefront gate of the FBCs.

Following this, a traditional CMOS gate process or a dual metal gateprocess may be applied to form the transistors. Ordinary tip implants,halo implants, formation of spacers prior to the implantation of themain source and drain regions, can occur. Implant masks may be appliedto allow separate implants for the memory and logic areas. Additionally,as is often the case following the deposition of a metal gate,polysilicon may be deposited to permit the subsequent formation of asilicide.

Referring to the plan view of FIG. 10, the n well 45 previously shownfor the memory array is again illustrated. The diffusion bodies 42 areshown along with the completed front gates 66 which act as word lines ina memory. As previously mentioned, the p region underlying the BOX layerfor the memory section, is negatively biased. This may be done byproviding a p well tap 65 which is most easily fabricated in the bulksilicon. A portion of the p well may be exposed during the step shown inFIG. 4, allowing subsequent access to the p well for the p well tap 65.

Thus, a method of fabricating a memory on an SOI substrate where thelogic transistors are formed in a bulk substrate is described.

1. A method for fabricating a memory on a silicon-on-insulator (SOI)substrate comprising: forming a protective mask over a first region ofan SOI layer from which memory cells are to fabricated; removing the SOIlayer and an underlying insulator in second regions of the substratewhere logic transistors are to be fabricated, to expose an underlyingbulk silicon substrate; and growing the exposed bulk silicon substrateto a level approximately equal to the level of the SOI layer in thefirst regions.
 2. The method of claim 1, where the bulk siliconsubstrate is a p type silicon and where either before or after the stepsof claim 1 the following occurs: forming an n well and an overlying pwell beneath in the first region; and forming p wells and n wells in thesecond regions.
 3. The method of claim 2, including: forming a tap tothe first region from one of the second regions.
 4. The method of claim2, including: forming a plurality of bodies in the first region from theSOI layer, for use in floating body memory cells.
 5. The method of claim4, including: forming first fins from the bulk silicon in the p wells ofthe second regions, for n channel transistors.
 6. The method defined byclaim 5, including: forming second fins from the bulk silicon in the nwells of the second regions, for p channel transistors.
 7. The method ofclaim 1, where the bulk silicon is a p type silicon and where eitherbefore or after the steps of claim 1 the following occurs: forming adeep n well in the second regions; and forming overlying p wells andoverlying n wells over the deep n well in the second regions.
 8. Themethod of claim 7, including: forming a tap to the p type bulk siliconin one of the second regions.
 9. The method of claim 8, including:forming bodies from the SOI layer in the first region for floating bodymemory cells.
 10. The method of claim 9, including: forming first finsin the n wells of the second regions from the bulk silicon for use in pchannel transistors.
 11. The method of claim 10, including: formingsecond fins in the p wells of the second regions from the bulk siliconfor use in n channel transistors.
 12. A method for fabricating anintegrated circuit (IC) having a memory array and logic devices on abulk silicon substrate comprising: providing a bulk silicon substrate;protecting first regions of the substrate while implanting oxygen atomsinto second regions to form a buried silicon oxide layer with anoverlying silicon-on-insulator (SOI) layer; forming floating bodies forfloating body memory cells from the SOI layer in the second regions; andeither before or after the above steps: forming n wells and p wells inthe first regions; forming first fins in the n regions from the bulksilicon for p channel transistors; forming second fins in the p wellsfrom the bulk silicon for n channel transistors.
 13. The method of claim12, wherein a p doped silicon underlies the oxide layer in the secondregion; and forming a tap to the p type silicon to allow biasing for thefloating body memory cells.
 14. The method of claim 13, including:forming a deep n well underlying the n wells and p wells of the firstregions.
 15. The method of claim 12, wherein the bulk silicon substratecomprises a p type silicon and including: forming an n well andoverlying p well in the second region.
 16. The method of claim 15,including: forming a contact to the p well beneath the second region fornegatively biasing that p well.
 17. An integrated circuit comprising: amemory section having a plurality of monocrystalline silicon bodiesdisposed on an insulator; and a plurality of logic devices comprising aplurality of fins integral with a bulk silicon underlying the insulator.18. The integrated circuit of claim 17, including a tap electricallyconnected to a p type region disposed beneath the insulator underlyingthe memory section, for biasing the memory section.
 19. The integratedcircuit of claim 18, wherein a first plurality of the logic devices areformed in n wells of the bulk silicon and a second plurality of logicdevices are formed in p wells of the bulk silicon.
 20. The integratedcircuit of claim 17, wherein a first plurality of the logic devices areformed in n wells of the bulk silicon and a second plurality of logicdevices are formed in p wells of the bulk silicon.